The present invention relates to a semiconductor memory device such as an electrically programmable nonvolatile memory with redundant memory cells for replacement of defective memory cells, and to the testing of such a semiconductor memory device.
There are various types of electrically programmable nonvolatile memory, including one-time programmable (OTP) read-only memory (ROM), which can be programmed but not erased; erasable programmable read-only memory (EPROM), which can be erased by exposure to ultraviolet light; and electrically erasable programmable read-only memory (EEPROM), which can be both programmed and erased electrically. An OTP ROM and an EPROM may be structurally the same, but the EPROM is housed in a package that admits ultraviolet light, while the OTP ROM is housed in a package that does not admit ultraviolet light. In this case, the data in an OTP ROM are erasable at the factory, before the device is packaged, but cannot be erased once the device has been shipped as a product. An OTP ROM is typically enclosed in an inexpensive plastic package, while an EPROM requires a more expensive windowed ceramic package.
Incidentally, OTP ROM is sometimes referred to by various other names, such as PROM (programmable ROM).
FIG. 8 shows a block diagram of a conventional OTP ROM or EPROM device. The device comprises a main cell array 10, an address buffer (AD. BUF.) 11, a plurality of address input terminals 12, a row decoder (DEC.) 13, a plurality of word lines 14, a column (COL.) decoder 15, a column switch circuit 16, a plurality of bit lines 17, a data input-output circuit 18, at least one data input-output terminal 19, a control circuit 20, a plurality of control signal input terminals 21, a redundancy fuse circuit (CKT) 22, a redundant address buffer (RED. AD. BUF.) 23, a redundancy decoder (RED. DEC.) 24, at least one redundant word line 25, a redundant cell array 26, and a non-select signal line 27.
The main cell array 10 and redundant cell array 26 are arrays of nonvolatile memory cells. Each memory cell comprises, for example, a field-effect transistor with a floating gate. The cell is programmed to the xe2x80x980xe2x80x99 state by injection of electrons into the floating gate, and erased to the xe2x80x981xe2x80x99 state by removal of electrons from the floating gate; these operations change the threshold voltage of the transistor. The programming operation is carried out by applying predetermined voltages to the memory cell; the erasing operation is carried out by exposure to ultraviolet light.
A memory cell is selected for programming or read access by selecting the bit line 17 and the word line 14 or redundant word line 25 to which the cell is connected. Only one word line 14 or redundant word line 25 is selected at a time, but when bit lines 17 are selected, n bit lines are selected simultaneously, where n is the number of data input-output terminals 19. Programming and read access are thus carried out n bits at a time; n is referred to as the data width.
The nonvolatile memory cells in the main cell array 10 will be referred to below as main memory cells, or simply as main cells. The nonvolatile memory cells in the redundant cell array 26 will be referred to as redundant memory cells, or simply as redundant cells.
The address signals received at the address input terminals 12 include a row address and a column address. Both the row and column addresses are stored simultaneously in the address buffer 11. Normally, the row decoder 13 decodes the row address and thereby selects one of the word lines 14. The column decoder 15 decodes the column address and supplies decoded signals to the column switch circuit 16, which selects a corresponding group of n bit lines 17. In this way n main memory cells are selected.
When data are programmed into the selected memory cells, n bits of data are supplied to the data input-output terminals 19 and passed in parallel through the data input-output circuit 18 to a programming circuit (not visible) in the column switch circuit 16, which places the data on the n selected bit lines 17. The data are programmed by the application of suitable voltages to the selected word line 14 and bit lines 17.
When data are read from the selected memory cells, n bits of data are passed in parallel from the memory cells through the column switch circuit 16 to sense amplifiers (not visible) in the data input-output circuit 18, then output from the data input-output terminals 19.
A word line 14 having one or more defective memory cells is replaced with a redundant word line 25 by cutting corresponding fuses (not visible) in the redundancy fuse circuit 22, thereby programming the redundancy fuse circuit 22 with the row address of the word line. This process is referred to as redundancy repair, and the row addresses programmed into the redundancy fuse circuit 22 will be referred to as redundancy repair addresses. After redundancy repair, when an address is received at the address input terminals 12 and stored in the address buffer 11, if the row address bits do not match any redundancy repair address, the row address is decoded by the row decoder 13 as described above to select a word line 14, but if the row address bits match a redundancy repair address, the redundancy decoder 24 drives the non-select signal line 27, thereby disables the row decoder 13, and selects a redundant word line 25. As a result, n redundant memory cells on the selected redundant word line 25 are accessed (programmed or read).
Before redundancy repair is performed, the redundant cell array 26 may need to be tested to check that the redundant cells themselves are not defective. During this test procedure, the control circuit 20 controls the redundancy decoder 24 to select the redundant word lines 25.
FIG. 9 is a flowchart of a conventional procedure for testing the memory cells and performing redundancy repair. The test procedure is carried out on a wafer on which a plurality of nonvolatile memory devices have been formed. The test apparatus, referred to below as a tester, has electrodes for accessing (xe2x80x98probingxe2x80x99) the address input terminals 12, data input-output terminals 19, and control signal input terminals 21 of each memory device on the wafer. The procedure comprises a first probing step S1, a fuse-programming step S2, an ultraviolet (UV) erasing step S3, a second probing step S4, a wafer baking step S5, a third probing step S6, and another ultraviolet erasing step S7. The first probing step S1 includes sub-steps S101 to S104. The second probing step S4 includes sub-steps S401 and S402. The third probing step S6 includes a single sub-step S601.
At the beginning of the procedure all memory cells are nominally in the erased (xe2x80x981xe2x80x99) state.
The first probing step S1 is carried out as follows. In sub-step S101, all memory cells in the main cell array 10 are read to check that they are in the xe2x80x981xe2x80x99 state. This is referred to as a xe2x80x981xe2x80x99 read test (a read test with the expected value xe2x80x981xe2x80x99). Next, in sub-step S102, all memory cells in the main cell array 10 are programmed to the xe2x80x980xe2x80x99 state and a xe2x80x980xe2x80x99 read test is performed (a read test with the expected value xe2x80x980xe2x80x99). The redundant memory cells are not tested at this stage.
Next, in sub-step S103, the row addresses of any defective main memory cells found in the preceding sub-steps are stored in the tester. Then in sub-step S104, the tester decides whether redundancy repair is necessary, and if necessary, whether it is feasible; that is, whether there are enough redundant word lines 25 to replace all the word lines 14 having defective memory cells.
If redundancy repair is necessary and feasible, then the redundancy fuse circuit 22 is programmed in step S2 by cutting fuses corresponding to the row addresses of the defective memory cells. This step replaces the defective main memory cells with redundant memory cells.
Following these steps, the wafer is exposed to ultraviolet light in step S3, erasing all memory cells to the xe2x80x981xe2x80x99 state.
In the second probing step S4, a xe2x80x981xe2x80x99 read test is performed in sub-step S401. All memory addresses are read. If any main memory cells have been replaced with redundant memory cells, then the redundant memory cells are read in place of the main memory cells. If the device passes this test, then xe2x80x980xe2x80x99 data are programmed at all memory addresses and a xe2x80x980xe2x80x99 read test is performed in sub-step S402.
At the end of step S2, four types of faults may be present in the device: (1) a main memory cell that cannot be erased to xe2x80x981xe2x80x99 (is stuck at xe2x80x980xe2x80x99) and has not been replaced by a redundant memory cell, possibly because the cell was not detected by the xe2x80x981xe2x80x99 read test in the first probing step, but more often because of unsuccessful fuse programming; (2) a main memory cell that cannot be programmed to xe2x80x980xe2x80x99 (is stuck at xe2x80x981xe2x80x99) and has not been replaced by a redundant memory cell, usually because of unsuccessful fuse programming; (3) a main memory cell replaced by a redundant memory cell that cannot be erased to xe2x80x981;xe2x80x99 (4) a main memory cell replaced by a redundant memory cell that cannot be programmed to xe2x80x980.xe2x80x99
Substantially all of these errors are detected by the xe2x80x981xe2x80x99 read test and xe2x80x980xe2x80x99 read test performed in the second probing step S4. Devices that pass these two tests are programmed to xe2x80x980xe2x80x99 at all memory addresses.
After the baking process in step S5, the third probing step S6 is carried out. The purpose of this probing step is to detect data retention faults. If, as explained above, a nonvolatile memory cell is programmed to xe2x80x980xe2x80x99 by injecting electrons into its floating gate, a data retention fault may occur due to slow leakage of the electrons from the floating gate. Baking accelerates the leakage process, so that data retention faults can be found more easily.
The third probing step S6 consists of a xe2x80x980xe2x80x99 read test (sub-step S601) performed at all memory addresses. Devices that fail this test, or fail either of the tests in the second probing step S4, or have too many bad main memory cells to be repaired, are marked as defective.
In step S7, the wafer is exposed to ultraviolet light to erase all data to xe2x80x981xe2x80x99 again, after which the wafer proceeds to further processing.
The procedure in FIG. 9 requires three separate wafer probing steps: one (S1) to identify the need for and feasibility of redundancy repair, another (S4) to detect faults of types (1) to (4) above, and yet another (S6) to detect data retention faults.
Unfortunately, wafer probing is relatively expensive. The problem is that fewer memory devices can be tested simultaneously during wafer probing than after the devices have been separated and packaged, and each wafer probing process takes time, because all addresses must be accessed. The total cost of three wafer probing steps contributes significantly to the unit cost of the memory device, especially when the device is an inexpensive OTP ROM.
FIG. 10 shows another conventional testing procedure that reduces the number of wafer probing steps from three to two. The procedure includes a first probing step S1, a fuse-programming step S2, a baking step S3, a second probing step S4, and an ultraviolet erasing step S5. The first probing step S1 includes sub-steps S11 to S17. The second probing step S4 includes a single sub-step S41.
The first probing step S1 begins with a xe2x80x981xe2x80x99 read test of all redundant (RED.) memory cells (sub-step S11). Next, all redundant memory cells are programmed to xe2x80x980,xe2x80x99 and a xe2x80x980xe2x80x99 read test is performed on them (sub-step S12). The addresses of any defective redundant cells found in these tests are stored in the tester (sub-step S13).
The first probing step continues with a xe2x80x981xe2x80x99 read test of all main memory cells (sub-step S14). Next, all main memory cells are programmed to xe2x80x980,xe2x80x99 and a xe2x80x980xe2x80x99 read test is performed on them (sub-step S15). The addresses of any defective main cells found in these tests are stored in the tester (sub-step S16).
From the stored addresses of the defective memory cells, the tester decides whether all of the defective main cells can be replaced with non-defective redundant cells (sub-step S17). This completes the first probing step.
If redundancy repair is necessary and feasible, the redundancy fuse circuit 22 is programmed by cutting fuses in step S2. By programming the row addresses of the defective main memory cells into the redundancy fuse circuit 22, this step replaces the defective main memory cells with non-defective redundant memory cells. At the end of this step, since all memory cells were programmed to xe2x80x980xe2x80x99 in sub-steps S12 and S15 of the first probing step S1, all-zero data should be readable from all addresses.
In step S3, the wafer is baked to accelerate leakage of programmed data from faulty memory cells.
In the second probing step S4, data retention is tested by performing a xe2x80x980xe2x80x99 read test (sub-step S41).
Finally, the wafer is exposed to ultraviolet light to erase all data to xe2x80x981xe2x80x99 in step S5.
Of the various types of faults mentioned earlier, this test procedure detects data retention faults, and stuck-at-xe2x80x981xe2x80x99 faults in main memory cells (2) and redundant memory cells (4), but it does not detect stuck-at-xe2x80x980xe2x80x99 faults reliably, because no xe2x80x981xe2x80x99 read test is performed after ultraviolet erasure. Faults of types (1) and (3) may thus remain undetected, especially if they are due to unsuccessful fuse programming.
An object of the present invention is to provide a semiconductor memory device that can be inexpensively tested to detect both stuck-at-xe2x80x980xe2x80x99 faults and stuck-at-xe2x80x981xe2x80x99 faults after redundancy repair.
Another object of the invention is to provide an inexpensive test method for the invented semiconductor memory device.
The invented semiconductor memory device has a main cell array, a redundant cell array, a first selection circuit for selecting memory cells in the main cell array in response to external address input, and a second selection circuit, programmable with at least one redundancy repair address, for selecting memory cells in the redundant cell array when the external address input matches the redundancy repair address.
The memory device also has a readout circuit for reading the redundancy repair address from the second selection circuit, a spare cell array, and a third selection circuit for selecting memory cells in the spare cell array. The spare cell array is used for independent storage of each redundancy repair address programmed into the second selection circuit.
The memory device furthermore has a data output circuit for output of the data stored in the selected memory cells in the main cell array and redundant cell array, and for output of redundancy repair test data. These test data may simply be the redundancy repair addresses read by the readout circuit, and the redundancy repair addresses stored in the spare cell array. Alternatively, the test data may be comparison result data generated by comparing the redundancy repair addresses read by the readout circuit with corresponding redundancy repair address data stored in the spare cell array, the comparison being performed by a comparison circuit within the memory device.
The invented method of testing the invented semiconductor memory device includes the steps of storing a redundancy repair address in the spare cell array, programming the redundancy repair address into the second selection circuit, reading the redundancy repair address from the second selection circuit, reading the redundancy repair address from the spare cell array, and comparing the two redundancy repair addresses. The comparison may be performed inside or outside the memory device.